1. Field of the Invention
This invention relates to an insulated gate field effect transistor of the self-aligned type, (otherwise called a self-aligned IGFET), especially to a self-aligned IGFET with an extended gate electrode end.
2. Description of the Prior Art
Self-aligned IGFETS have been manufactured using silicon gate technology which can provide high production yields and high density when incorporated in integrated circuits. According to this silicon gate technology, the surface of a semiconductor substrate is exposed at its active region including a source region, a drain region and a channel region. A new gate insulator is formed on the active region by thermal oxidation. A silicon gate electrode is then formed on an area including the channel region. Then, the new gate insulator is etched away only at the source and drain regions, while leaving it under the silicon gate electrode. The next process is to diffuse an impurity into the exposed areas of the substrate to form the source and drain regions using the silicon gate electrode as a diffusion mask. It is therefore not necessary to align the gate electrode with the source and drain regions. Thus, the gate electrode is automatically aligned. Accordingly, the silicon gate technology is often referred to as being of the self-aligned type.
Referring to FIG. 1, a plan view is shown of the structure of an IGFET as incorporated in an integrated circuit. The source region 5 is opposite to the drain region 6 at the channel region 7. The extended regions 5a and 6a of the source and drain regions 5 and 6 are included to provide conductive paths. The gate electrode 4 is extended in another direction for the wiring interconnective and in the same direction as that of source and drain regions 5a and 6a by "d" on the field oxide layer 2. The distance "d" is for ensuring a predetermined channel width in spite of mechanical alignment error. The distance "a" is for the same purpose. Therefore, the distance "c" between the extended regions 5a and 6a is controlled by the gate width "b" and the error "2a".
FIG. 2, is a partial cross section of the IGFET shown in FIG. 1 at the line I--I.
In FIG. 2, the substrate 1 is typically comprised of silicon. The thickness of the field oxide layer 2 is typically about 1 micron meter. The gate insulator 3 is typically comprised of silicon dioxide and is about 1000 angstroms thick. An insulating layer 2 covering the surface of the substrate 1 is not shown in FIG. 1 for the sake of simplicity.
U.S. Pat. No. 3,699,646 discloses a method for simultaneously completing the formation of a contact, a wiring interconnection, a gate and a source or drain.
The method disclosed in the above patent is used in conjunction with the process of manufacturing the IGFET transistor circuit configuration of the present invention.